Apparatus and method for discrete test access control of multiple cores

ABSTRACT

An electronic circuit includes multiple computational cores. A test access protocol machine with a core address register and a signal routing control circuit addresses a selected computational core as specified by the core address register and routes output test data from the selected computational core.

BRIEF DESCRIPTION OF THE INVENTION

This invention relates generally to digital circuits. More particularly,this invention relates to test access techniques for discretelyaccessing multiple computational cores.

BACKGROUND OF THE INVENTION

A semiconductor intellectual property (IP) core, IP block, or corerefers to a reusable unit of logic, cell, or chip layout design that isowned by an entity. The core may be licensed to another party or can beowned and used by a single party. In digital logic applications, coresare typically offered as generic gate netlists. The netlist is a Booleanrepresentation of the core's logical function. Some vendors offersynthesizable versions of their cores. Synthesizable cores are deliveredin a hardware description language, such as Verilog or VHDL, permittingcustomer modification at the functional level.

Cores are implemented with physical circuits. Testing of physicalcircuits is typically performed in accordance with a Test AccessProtocol (TAP). JTAG, an acronym for Joint Test Action Group, is thename used for the IEEE 1149.1 standard entitled Standard Test AccessPort and Boundary-Scan Architecture. While designed for printed circuitboards, JTAG is commonly used for testing sub-blocks of integratedcircuits and is also used for debugging embedded systems. When used as adebugging tool, an in-circuit emulator, which in turn uses JTAG as thetransport mechanism, enables a programmer to access an on-chip debugmodule which is integrated into the core. The debug module enables theprogrammer to debug the software of an embedded system.

JTAG supports the serial scan of test data between multiple cores withina single system. In order to communicate with a single core, the TAPcontroller serially scans through all of the TAP chains. Non-addressedcores can be placed in a bypass mode to minimize the total length of theTAP chain. However, placing non-addressed cores into bypass mode incursan overhead cost.

In view of the foregoing, it would be desirable to provide an improvedtechnique for accessing and testing individual cores in a multiple coresystem.

SUMMARY OF THE INVENTION

The invention includes an electronic circuit with multiple computationalcores. A test access protocol machine with a core address register and asignal routing control circuit addresses a selected computational coreas specified by the core address register and routes output test datafrom the selected computational core.

A computer readable medium includes executable instructions to describemultiple computational cores. Executable instructions also specify atest access protocol machine with a core address register and a signalrouting control circuit to address a selected computational core asspecified by the core address register. Output test data is routed fromthe selected computational core in accordance with signal routingcontrol signals from the signal routing control circuit.

The invention also includes a method of loading a core addressspecifying a single core of a multiple core system. Signal routingcontrol signals are enabled. Output test data from the single corespecified by the core address is routed in accordance with the signalrouting control signals.

The invention also includes a test access protocol machine with a coreaddress register and a signal routing control circuit to address aselected computational core of a set of computational cores. Theselected computational core is specified by the core address register.Test data from the selected computational core is routed in accordancewith signal routing control signals from the signal routing controlcircuit.

The invention also includes a method of forming a test access protocolmachine to access a single core of a multiple core system. The testaccess protocol machine is operated in a first state wherein output testdata from the single core is directly delivered to the test accessprotocol state machine and in a second state wherein output test datafrom the single core is initially routed through at least one additionalcore of the multiple core system prior to being delivered to the testaccess protocol state machine.

BRIEF DESCRIPTION OF THE FIGURES

The invention is more fully appreciated in connection with the followingdetailed description taken in conjunction with the accompanyingdrawings, in which:

FIG. 1 illustrates a system configured in accordance with an embodimentof the invention.

FIG. 2 illustrates processing operations associated with an embodimentof the invention.

Like reference numerals refer to corresponding parts throughout theseveral views of the drawings.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1 illustrates a system 100 configured in accordance with anembodiment of the invention. The system 100 includes a set of IP cores,computational cores, or cores 102_A through 102_D. The system 100 alsoincludes a test access controller 104. The test access controller 104includes a standard TAP state machine 106, which is configured toperform operations in accordance with the JTAG standard. In addition toimplementing standard JTAG operations, the TAP state machine 106 isconfigured to include a core address register 108 and a signal routingcontrol circuit 110 to implement operations of the invention.Alternately, the core address register 108 and the signal routingcontrol circuit 110 may interface with the TAP state machine 106.Reference herein to a TAP machine or TAP state machine contemplateseither embodiment.

The core address register stores the address of an individual core.Thus, the invention allows, for example, core 102_A to be addressedwithout accessing cores 102_B, 102_C and 102_D. The core addressregister may be loaded from a probe (not shown). In particular, a probeapplies a core address to a node associated with the TAP state machine106. Alternately, the core address register is loaded from a memory mapwithin an individual core 102.

The test access controller 104 includes additional circuitry toimplement operations of the invention. In particular, a set of logicalAND gates 112_A, 112_B, 112_C and 112_D are used to control test clockaccess to individual cores. When the test clock is enabled, anindividual core drives output data. Otherwise, no output data isproduced by a non-addressed core. Multiplexers 114_A, 114_B, 114_C and114_D facilitate daisy chain routing of output data, as discussed below.Multiplexer 116 operates to select test data from an individuallyaddressed core, as discussed below. The logical AND gates 112, themultiplexers 114 and the multiplexer 116 are controlled by the signalrouting control circuit 110.

The signal routing control circuit 110 generates signal routing controlsignals to coordinate the routing of test data from a selected core. Inone embodiment of the invention, the test data is routed directly fromthe selected core (e.g., 102_A) through the TAP state machine 106without traversing additional cores (e.g., 102_B, 102_C or 102_D).Alternately, the test data is routed from the selected core (e.g.,102_B) through an arbitrary set of cores (e.g., 102_C or 102_C and102_D). This arbitrary daisy chaining still requires that cores beadjacent in the embodiment of FIG. 1. However, this limitation may beavoided by using additional multiplexers.

As shown in the figure, a Test Data In (TDI) signal is applied to thetest access controller 104. The TAP state machine 106 routes the TDIsignal to each core, as shown with long dashed lines 120. The testaccess controller 104 also receives a test clock signal TCK, which isalso routed to each of the cores, via the TAP state machine 106, viasolid lines 122. More particularly, the clock signal is initially routedto the logical AND gate 112 associated with a core.

Consider an example wherein the core address register stores an addressthat specifies core 102_D. In this example, the signal routing controlcircuit 110 generates a digital high signal on line 124. The logical ANDgate 112_D receives the TCK signal on line 122 and the digital highsignal on line 124. Thus, the core 102_D receives the TCK signal andgenerates test data on short dashed line 126. The test data is appliedto the multiplexer 116. The signal routing control circuit applies acontrol signal to the multiplexer 116 such that the multiplexer selectsand passes the test data to the TAP state machine 106. In this example,the signal routing control circuit 110 only enables core 102_D togenerate test data. Accordingly, a single core of the multiple coresystem has been accessed to produce test data without serial scanningthrough additional cores.

The invention is also operative to access a single core and thenserially route test data through one or more additional cores. Considera case in which core 102_C is to be accessed. In this case, the signalrouting control circuit 110 generates a digital high signal to logicalAND gate 112_C via line 128. This allows the clock TCK to drive testdata from core 102_C over line 126.

A control signal from the signal routing control circuit 110 may then beused to select the output data of line 126 at multiplexer 114_C. Thus,the test data is driven through core 102_D. If the test data is not tobe driven through core 102_D, it may be directly routed to the TAP statemachine via a select signal from that signal routing control circuit110, which is applied to multiplexer 116. Using control signals from thesignal routing control circuit 110 therefore allows arbitrary routing oftest data through one or more daisy chained cores.

FIG. 2 illustrates processing operations associated with an embodimentof the invention. Initially, a core address register is loaded 200. Aspreviously indicated, the loading operation may be implemented from aprobe or a memory map within a core 102.

Signal routing control signals are then enabled 202. As previouslyindicated, the signal routing control signals include signals forapplication to one or more logical AND gates 112_A, 112_B, 112_C and112_D, multiplexer select signals for multiplexers 112_A, 112_B, 112_Cand 112_D, and multiplexer select signals for multiplexer 116.

The next processing operation of FIG. 2 is to route test data from aselected computation core 204. Various examples of this operation arediscussed above. Optionally, the test data may be routed to additionalcomputational cores 206. As discussed above, arbitrary daisy chaining toadditional adjacent cores may be implemented in accordance with anembodiment of the invention.

Thus, the invention provides a JTAG addressable block in a multiple coresystem to control the connection of the TAP chain between a JTAG probeand each of the cores. This allows for more efficient communication withindividual cores.

The invention allows for individually addressable cores without usingadditional pins. The invention facilitates traditional daisy chainedconnections or single core access.

While various embodiments of the invention have been described above, itshould be understood that they have been presented by way of example,and not limitation. It will be apparent to persons skilled in therelevant computer arts that various changes in form and detail can bemade therein without departing from the scope of the invention. Forexample, in addition to using hardware (e.g., within or coupled to aCentral Processing Unit (“CPU”), microprocessor, microcontroller,digital signal processor, processor core, System on chip (“SOC”), or anyother device), implementations may also be embodied in software (e.g.,computer readable code, program code, and/or instructions disposed inany form, such as source, object or machine language) disposed, forexample, in a computer usable (e.g., readable) medium configured tostore the software. Such software can enable, for example, the function,fabrication, modeling, simulation, description and/or testing of theapparatus and methods described herein. For example, this can beaccomplished through the use of general programming languages (e.g., C,C++), hardware description languages (HDL) including Verilog HDL, VHDL,and so on, or other available programs. Such software can be disposed inany known computer usable medium such as semiconductor, magnetic disk,or optical disc (e.g., CD-ROM, DVD-ROM, etc.). The software can also bedisposed as a computer data signal embodied in a computer usable (e.g.,readable) transmission medium (e.g., carrier wave or any other mediumincluding digital, optical, or analog-based medium). Embodiments of thepresent invention may include methods of providing the apparatusdescribed herein by providing software describing the apparatus andsubsequently transmitting the software as a computer data signal over acommunication network including the Internet and intranets.

It is understood that the apparatus and method described herein may beincluded in a semiconductor intellectual property core, such as amicroprocessor core (e.g., embodied in HDL) and transformed to hardwarein the production of integrated circuits. Additionally, the apparatusand methods described herein may be embodied as a combination ofhardware and software. Thus, the present invention should not be limitedby any of the above-described exemplary embodiments, but should bedefined only in accordance with the following claims and theirequivalents.

1. An electronic circuit, comprising: multiple computational cores; anda test access protocol machine with a core address register and a signalrouting control circuit to address a selected computational core asspecified by the core address register and route output test data fromthe selected computational core in accordance with signal routingcontrol signals from the signal routing control circuit.
 2. Theelectronic circuit of claim 1 wherein the signal routing control circuitgenerates an enable signal to facilitate application of a test clocksignal to the selected computational core.
 3. The electronic circuit ofclaim 1 wherein the signal routing control circuit generates amultiplexer control signal to coordinate the routing of the output testdata.
 4. The electronic circuit of claim 1 wherein the signal routingcontrol circuit generates an enable signal to facilitate application ofa test clock signal to each of the multiple computational cores.
 5. Theelectronic circuit of claim 4 wherein the signal routing control circuitgenerates multiplexer control signals to coordinate arbitrary daisychain routing of output test data through a plurality of multiplecomputational cores.
 6. The electronic circuit of claim 1 furthercomprising a probe node to receive an address for storage in the coreaddress register.
 7. The electronic circuit of claim 1 wherein anaddress is written to the core address register from one of the multiplecomputational cores.
 8. A computer readable medium, comprisingexecutable instructions to describe: multiple computational cores; and atest access protocol machine with a core address register and a signalrouting control circuit to address a selected computational core asspecified by the core address register and route output test data fromthe selected computational core in accordance with signal routingcontrol signals from the signal routing control circuit.
 9. The computerreadable medium of claim 8 wherein the executable instructions todescribe the signal routing control circuit produce an enable signal tofacilitate application of a test clock signal to the selectedcomputational core.
 10. The computer readable medium of claim 8 whereinthe executable instructions to describe the signal routing controlcircuit produce a multiplexer control signal to coordinate the routingof the output test data.
 11. The computer readable medium of claim 8wherein the executable instructions to describe the signal routingcontrol circuit produce an enable signal to facilitate application of atest clock signal to each of the multiple computational cores.
 12. Thecomputer readable medium of claim 11 wherein the executable instructionsto describe the signal routing control circuit produce multiplexercontrol signals to coordinate arbitrary daisy chain routing of outputtest data through a plurality of multiple computational cores.
 13. Thecomputer readable medium of claim 8 further comprising executableinstructions to define a probe node to receive an address for storage inthe core address register.
 14. The computer readable medium of claim 8wherein an address is written to the core address register from amultiple computational core.
 15. The computer readable medium of claim 8wherein the executable instructions are selected from a HardwareDescription Language (HDL), Verilog, and VHDL.
 16. The computer readablemedium of claim 8 wherein the executable instructions are transmitted asa computer data signal.
 17. A method, comprising: loading a core addressspecifying a single core of a multiple core system; enabling signalrouting control signals; and routing output test data from the singlecore specified by the core address in accordance with the signal routingcontrol signals.
 18. The method of claim 17 wherein loading includesloading the core address from a probe.
 19. The method of claim 17wherein loading includes loading the core address from a core of themultiple core system.
 20. The method of claim 17 wherein enablingincludes producing an enable signal to facilitate application of a testclock signal to the single core.
 21. The method of claim 17 whereinenabling includes producing multiplexer control signals to coordinatethe routing of the output test data.
 22. The method of claim 17 whereinenabling includes producing an enable signal to facilitate applicationof a test clock signal to each of the cores of the multiple core system.23. The method of claim 17 wherein enabling includes producingmultiplexer control signals to coordinate arbitrary daisy chain routingof the output test data through a plurality of the cores of the multiplecore system.
 24. An electronic circuit, comprising: a test accessprotocol machine with a core address register and a signal routingcontrol circuit to address a selected computational core, of a set ofcomputational cores, as specified by the core address register and routeoutput test data from the selected computational core in accordance withsignal routing control signals from the signal routing control circuit.25. The electronic circuit of claim 24 wherein the signal routingcontrol circuit generates an enable signal to facilitate application ofa test clock signal to the selected computational core.
 26. Theelectronic circuit of claim 24 wherein the signal routing controlcircuit generates a multiplexer control signal to coordinate the routingof the output test data.
 27. A method, comprising: forming a test accessprotocol machine to access a single core of a multiple core system; andoperating the test access protocol machine in a first state whereinoutput test data from the single core is directly delivered to the testaccess protocol state machine and in a second state wherein output testdata from the single core is initially routed through at least oneadditional core of the multiple core system prior to being delivered tothe test access protocol state machine.
 28. The method of claim 27wherein operating includes generating a first multiplexer control signalto establish the first state and producing a second set of multiplexercontrol signals to establish the second state.
 29. The method of claim27 further comprising loading an address for the single core into thetest access protocol state machine.